1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to an insulated gate field effect transistor characterized by its gate electrode, and to a method of fabricating the same.
2. Description of Related Art
In insulated gate field effect transistors used for current semiconductor integrated circuits, a polycrystalline silicon layer doped with high concentration of impurities is generally used as a gate electrode in order to decrease the resistance. In a semiconductor process used for CMOS circuits (Complimentary MOSFET circuits), N-type polycrystalline silicon and P-type polycrystalline silicon are respectively used for an N-channel MOSFET (NMOSFET) and a P-channel MOSFET (PMOSFET) as gate electrode materials for balancing the characteristics. Generally, a high-melting-point metal silicide layer is formed in the upper layer of the gate electrode in order to further decrease the resistance.
However, depletion occurs in the polysilicon layer of the gate electrode although the polysilicon layer is doped with high concentration of impurities. Occurrence of depletion is equivalent to the condition in which a capacitance is inserted into the gate electrode in series, thereby decreasing an effective electric field applied to a channel. As a result, the current drive capability of the MOSFET decreases. It is difficult to decrease the resistance of the entire gate electrode to 5 xcexa9/ or less even if a silicide layer is laminated on the polycrystalline silicon layer. In the case of miniaturizing the device to the 0.1 micron generation, since the thickness of the gate electrode must be reduced, the gate electrode is required to have a specific resistance of about 30 xcexcxcexa9xc2x7cm or less.
The work functions of the N-type polycrystalline silicon layer and the P-type polycrystalline silicon layer, which are directly in contact with the gate insulating layer, are respectively 4.15 eV and 5.25 eV. The work functions of these layers significantly differ from the center of the bandgap of silicon (4.61 eV). Such a large difference results in an increase in the absolute value of a flat band voltage VFB in a MOS capacitor formed of a metal-insulating layer-semiconductor (signs differ between NMOSFET and PMOSFET). Therefore, in such MOSFETS, an optimum value of the impurity concentration in the channel must be shifted to the high concentration side in order to control a threshold value VTH. The channel with high-concentration impurities is significantly influenced by carrier scattering due to impurities. As a result, carrier mobility in the channel decreases. This means a decrease in the current drive capability of the MOSFET, thereby significantly affecting the response characteristics of the circuit.
In order to solve these problems, low-resistance gate electrode materials which do not cause gate depletion to occur and have various work functions have been proposed. For example, a structure using a titanium nitride (TiN) layer is disclosed by Jeong-Mo Hwang, et al. (in IEDM Technical Digest, 1992, page 345), and a structure using a beta-tantalum (xcex2-Ta) layer is disclosed by Ushiki, et al. (in IEDM Technical Digest, 1996, page 117).
The following is pointed out for the gate electrode having a TiN layer formed on a gate insulating layer used in the N-type or P-type MOSFET. Since the TiN layer has a relatively high specific resistance of about 200 xcexcxcexa9xc2x7cm, a metal (tungsten, for example) layer is laminated on the TiN layer in order to decrease resistance of the gate electrode. The work function of the TiN layer (4.7 to 4.8 eV) is close to the center of the bandgap of silicon (4.61 eV), as reported by Jeong-Mo Hwang, et al., whereby a significant effect is expected in view of the threshold value control.
However, according to this configuration example, since the TiN layer and the tungsten layer are dissolved in a chemical solution such as a hydrogen peroxide aqueous solution and sulfuric acid, it is very difficult to clean the gate electrode layer after etching. Therefore, devices having this structure cannot be fabricated at high yield.
The following is pointed out for the gate electrode having a tantalum layer formed on the gate insulating layer used in the N-type or P-type MOSFET. According to this configuration example, only a beta-tantalum layer exhibiting high resistance as a metal (specific resistance: about 160 xcexcxcexa9xc2x7cm) can be deposited as the tantalum layer, whereby the resistance of the gate electrode relatively increases. Moreover, since the work function of the beta-tantalum layer significantly differs from the center of the bandgap of silicon, the threshold value is shifted to the low threshold side, thereby resulting in an imbalance threshold between the NMOSFET and the PMOSFET.
An object of the present invention is to provide a semiconductor device which exhibits high current drive capability and can be fabricated at high yield, and a method of fabricating the same.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
first and second impurity diffusion layers which are provided in a semiconductor layer and form a source region and a drain region;
a channel region formed between the first and second impurity diffusion layers;
a gate insulating layer formed at least on the channel region; and
a gate electrode formed on the gate insulating layer,
wherein the gate electrode includes a tantalum nitride layer formed in a region which is in contact with at least the gate insulating layer, and a tantalum layer formed over the tantalum nitride layer.
The semiconductor device according to the present invention has the following effects.
(1) The gate electrode includes the tantalum nitride layer formed so as to be in contact with the gate insulating layer. The work function of the tantalum nitride layer is approximately 4.5 eV, which is extremely close to the center of the bandgap of silicon. As a result, the absolute value of the flat band voltage in a capacitor consisting of metal-insulating layer-silicon can be decreased. This eliminates the need for increasing the concentration of impurities doped into the channel region in order to obtain an appropriate threshold value. Therefore, a decrease in carrier mobility can be prevented, whereby an insulated gate field effect transistor exhibiting high current drive capability can be obtained at high yield.
(2) As described in the above (1), the work function of the tantalum nitride layer is extremely close to the center of the bandgap of silicon. Because of this, the difference in the absolute values of the flat band voltages between an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor can be significantly reduced in a capacitor consisting of metal-insulating layer-silicon, although the same type of electrode is used for both transistors. As a result, in a complementary semiconductor device including both an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the threshold balance between these transistors can be accurately and easily controlled. Moreover, use of the same electrodes reduces the fabrication steps in comparison with the above-described conventional bipolar polysilicon gates. Furthermore, in the case of a complementary semiconductor device using a fully depleted SOI (Silicon On Insulator) structure or SON (Silicon On Nothing) structure, the absolute value of the threshold voltage can be reduced while preventing punch-through from occurring. This leads to advantages in miniaturization and low-voltage drive.
(3) The gate electrode includes at least the tantalum nitride layer, and the polysilicon layer is not in contact with the gate electrode. Therefore, depletion does not occur in the gate electrode. As a result, the gate electrode can prevent effective electric field applied to the channel region from reducing in comparison with the case of using a polysilicon layer. This also prevents a reduction in current drive capability.
(4) The tantalum nitride layer of the gate electrode exhibits higher chemical stability in comparison with a titanium nitride layer and the like. For example, the tantalum nitride layer exhibits excellent resistance to a chemical solution used to clean the gate electrode. As a result, devices can be fabricated at high yield.
(5) The tantalum layer of the gate electrode has lower resistance in comparison with the tantalum nitride layer, whereby conductivity of the gate electrode can be increased. The tantalum layer may be formed of body-centered cubic tantalum. Body-centered cubic tantalum exhibits a higher conductivity than beta-tantalum. Specifically, body-centered cubic tantalum can reduce the resistance of the gate electrode to about one-tenth of that in the case of using of beta-tantalum. Such a body-centered cubic tantalum layer may be heteroepitaxially grown by lattice matching with the tantalum nitride layer.
The present invention has various features as follows. These features also apply to a complementary semiconductor device and a method of fabricating a semiconductor device described later.
(A) The nitrogen/tantalum ratio (x) of the tantalum nitride layer denoted by TaNx may be 0.25 to 1.0 in view of conductivity and work function. In particular, the nitrogen/tantalum ratio (x) of the tantalum nitride layer denoted by TaNx can be about 0.5.
(B) The tantalum nitride layer may have a thickness of 1 nm to 50 nm, or 3 nm to 20 nm in view of heteroepitaxial growth of the tantalum layer and the like.
(C) The gate electrode may include a cap layer in the uppermost layer. The cap layer may be formed by using at least one material selected from TaNx, TaSixNy, TiNx, TiAlxNy, Si, and silicide of a transition metal. In the case where the cap layer is a tantalum nitride layer, each layer of the gate electrode can be easily and continuously formed by using the same apparatus (sputtering apparatus, for example).
(D) A silicide layer may be formed in exposed regions of the first and second impurity diffusion layers and on the upper side of the gate electrode. The presence of such a silicide layer increases conductivity of the impurity diffusion layers and the gate electrode.
(E) The semiconductor layer may have an SOI structure or SON structure. Alternatively, the semiconductor layer may be a silicon layer containing impurities at a concentration of 1017 cmxe2x88x923 or less, having a thickness one-third the gate length or less, and formed on a bulk semiconductor substrate containing impurities at a concentration of more than 1017 cmxe2x88x923.
The present invention can be suitably applied to a complementary semiconductor device, as described above. Specifically, a complementary semiconductor device according to a second aspect of the present invention comprises:
an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor,
wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor comprises:
first and second impurity diffusion layers which are provided in a semiconductor layer and form a source region and a drain region;
a channel region formed between the first and second impurity diffusion layers;
a gate insulating layer formed on the channel region; and
a gate electrode formed on the gate insulating layer,
wherein the gate electrode includes a tantalum nitride layer formed in a region which is in contact with at least the gate insulating layer, and a tantalum layer formed over the tantalum nitride layer.
According to this complementary semiconductor device, since the work function of the tantalum nitride layer is extremely close to the center of the bandgap of silicon, as described above, the absolute value of the flat band voltage can be reduced. This eliminates the need for increasing the concentration of impurities doped into the channel region in order to obtain an appropriate threshold value. Therefore, a decrease in carrier mobility can be prevented, whereby an insulated gate field effect transistor exhibiting high current drive capability can be obtained at high yield. Moreover, the threshold balance between the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor can be accurately and easily controlled although the same type of electrode is used for both transistors. Furthermore, in the case of a complementary semiconductor device using a fully depleted SOI structure or SON structure, the absolute value of the threshold voltage can be reduced while preventing punch-through from occurring. This ensures the achievement of miniaturization and low-voltage drive.
According to a third aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a) forming a gate insulating layer on a semiconductor layer;
(b) forming a gate electrode on the gate insulating layer by forming a tantalum nitride layer in a region in contact with at least the gate insulating layer and forming a tantalum layer over the tantalum nitride layer; and
(c) introducing impurities into the semiconductor layer to form first and second impurity diffusion layers which form a source region and a drain region.
The tantalum layer can be formed of body-centered cubic tantalum as described above. Body-centered cubic tantalum exhibits a higher conductivity than that of beta-tantalum. Such a body-centered cubic tantalum layer can be heteroepitaxially grown by lattice matching with the tantalum nitride layer.
The method of fabricating a semiconductor device according to the present invention has features as follows. These features also apply to a method of fabricating a complementary semiconductor device described later.
(A) The first and second impurity diffusion layers may be self-alignably formed by using the gate electrode as a mask in the step (c).
(B) The method may further comprise a step (e) in which a side-wall spacer is formed on each side of the gate electrode after the step (c).
(C) A silicide layer may be formed in exposed regions of the first and second impurity diffusion layers after the step (e).
(D) In the step (b), the tantalum nitride layer and the tantalum layer may be formed by sputtering. If the sputtering is carried out in the presence of xenon or krypton gas, the tantalum layer more reliably exhibits a body-centered cubic crystal structure. Moreover, the steps (a) and (b) may be carried out continuously without allowing the deposited films to be exposed to air.
According to a fourth aspect of the present invention, there is provided a method of fabricating a complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, comprising the steps of:
(a) forming a gate insulating layer on a semiconductor layer;
(b) forming a gate electrode on the gate insulating layer by forming a tantalum nitride layer in a region in contact with at least the gate insulating layer and forming a tantalum layer over the tantalum nitride layer; and
(c) introducing impurities into the semiconductor layer to form a source region and a drain region, comprising forming N-type first and second impurity diffusion layers for the N-channel insulated gate field effect transistor, and forming P-type first and second impurity diffusion layers for the P-channel insulated gate field effect transistor.